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25.1 Introduction use .net vs 2010 quick response code printing toproduce qr-code on .net Code128 The IEEE 802.11g s QR Code ISO/IEC18004 for .NET pecification [1], which was only ratified in June 2003, has become the most widely deployed wireless local area network (WLAN) standard today.

Its popularity is due in large part to its support for higher data rates while maintaining backwards compatibility to legacy IEEE 802.11b [2] WLANs. An IEEE 802.

11g device achieves the higher data rate when communicating with other 802.11g devices by using orthogonal frequency division multiplexing (OFDM) modulation. When communicating with legacy 802.

11b devices, it will revert back to either direct sequence spread spectrum (DSSS) or complementary code keying (CCK) modulation. The standard uses 83.5-MHz of available spectrum in the 2.

4-GHz band and allows for three non-overlapping channels. The data rates range from 1-2 Mbps using DSSS modulation, 5.5-11 Mbps using CCK modulation, and 6-54 Mbps using OFDM modulation.

As in the IEEE 802.11a specification [3], the OFDM in 802.11g uses 52 sub-carriers, each of which can be modulated with BPSK, QPSK, 16-QAM or 64-QAM.

The rapid adoption of IEEE 802.11g WLANs and their growing popularity in portable applications such as PDAs and cellphones highlighted the need for a low-cost, small form factor solution. This paper describes an integrated single-chip system-on-a-chip (SoC) that.

All authors curren tly affiliated with Atheros Communications All authors currently affiliated with Stanford University. 552 An 802.11g WLAN SoC can meet both the cost and form factor requirements by implementing all of the functions of an IEEE 802.11g WLAN system in a single 0.18- m CMOS die.

The integrated SoC combines the RF transceiver, analog baseband filters, data converters, digital baseband, physical layer (PHY), and medium access controller (MAC). The IC essentially converts the input RF signal to digital bits. In addition to reducing overall package cost, integration eliminates the area and power associated with driving package pins in a multi-chip implementation [4] [5].

Furthermore, the merging of the analog and digital blocks on the same chip enables a wide digital-analog interface that allows for the use of sophisticated digital signal processing and calibration techniques to mitigate analog and RF impairments [6]-[8]. These techniques include closed loop calibration of receiver DC offset, I/Q mismatch and transmitter carrier leak. However, SoC integration has significant challenges, such as noise isolation between noisy digital circuits and sensitive analog circuits.

Special care must be taken to minimize coupling between high-swing digital switching I/Os and RF circuits processing signals many orders of magnitude smaller. Section 25.2 of this paper addresses the overall SoC architecture and frequency plan.

Section 25.3 focusses on the RF transceiver blocks: receiver, transmitter and synthesizer. Specific circuits in the receiver and transmitter are examined.

Section 25.4 addresses advantages and challenges of SoC integration such as calibration. Finally, measurement results are shown in section 25.

5.. 25.2 Architecture The overall SoC bl ock diagram is shown in Fig. 25.1.

The chip receives the RF signal from the antenna and down-converts it to baseband using inphase (I) and quadrature (Q) filters and analog-to-digital converters (ADC). The digital processing of the ADC outputs is done in the physical layer (PHY) which interfaces with the Medium Access Controller (MAC). The MAC interfaces to the PCI bus which connects directly to the host computer.

In the transmitter, digital data from the host computer passes through the PCI bus, MAC, and PHY to drive a set of I and Q digital-to-analog converters (DACs). The DAC outputs are filtered and upconverted to RF. A single synthesizer generates the local oscillator (LO) signals for the receive and transmit blocks.

Analog circuits in the transceiver are configured to operate in the various modes using a control block.. Figure 25.1: SoC Block Diagram. An 802.11g WLAN SoC 553 The frequency plan QR Code for .NET of the transceiver, shown in Fig. 25.

2, uses a sliding intermediate frequency (IF), similar to the IEEE 802.11a frequency plan in [4] and [9]. This IF is not fixed in frequency but changes depending on the desired RF channel in the 2.

4-GHz band. This channel is first converted to an IF frequency at 1/3 the RF frequency using a local oscillator (LO) of 2/3 fRF. The IF signal is then down-converted to baseband using an LO of 1/3 fRF.

Only one synthesizer is required because the 1/3 fRF signal is generated using a simple divide-by-2 block from the 2/3 fRF signal. In addition, voltage controlled oscillator (VCO) pulling is avoided because the LO and the RF frequencies are approximately 800MHz apart..

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