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Copyright 1999 by John F. Wakerly Copying Prohibited in Software Integrated ANSI/AIM Code 39 in Software Copyright 1999 by John F. Wakerly Copying Prohibited




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Copyright 1999 by John F. Wakerly Copying Prohibited generate, create none none with none projects iPhone OS DO NOT COPY none none DO NOT COPY DO NOT COPY DO NOT COPY DO NOT COPY DO NOT COPY DO NOT COPY DO NOT COPY DO NOT COPY. 6 . Combinational Design Examples E2_L E1_L E0_L M3_L Figure 6-3 A combinational fixed-point to floatingpoint encoder. DO NOT COPY DO NOT COPY DO NOT COPY DO NOT COPY DO NOT COPY DO NOT COPY DO NOT COPY DO NOT COPY DO NOT COPY. 74x151. 74x148. 5 4 3 2 1. B10_L B9_L B8_L B7_L B6_L B5_L B4_L B3_L EI I7 13 12 11 10. I5 I4 I3 I2 I1 I0 A0 A1 A2 9 7 6. A 10 B 9 C B9_L B8_L B7_L B6_L B5_L D0 D1 2 D2 14 15. B4_L B3_L B2_L D4 14 D5 13 D6 12 D7 M2_L 74x151. B_L[10:0]. A B 9 C B8_L B7_L B6_L B5_L B4_L B3_L B2_L B1_L D0 D1 2 D2 D3 D4 14 D5 13 D6 12 D7 M1_L 74x151. A B 9 C B7_L B6_L B5_L B4_L B3_L B2_L B1_L B0_L D0 D1 2 D2 D3 D4 14 D5 13 D6 12 D7 M0_L Copyright 1999 by John F. Wakerly Copying Prohibited Section 6.1 Building-Block Design Examples I7 (highest priority) through I0 connected to b10 b3. We can use the priority encoder s A2 A0 outputs directly as the exponent, as long as the no-1-found case produces A2 A0 = 000. Picking off four bits sounds like a selecting or multiplexing operation.

The 3-bit exponent determines which four bits of B we pick off, so we can use the exponent bits to control an 8-input, 4-bit multiplexer that selects the appropriate four bits of B to form M. An MSI circuit that results from these ideas is shown in Figure 6-3. It contains several optimizations: Since the available MSI priority encoder, the 74x148, has active-low inputs, the input number B is assumed to be available on an active-low bus B_L[10:0].

If only an active-high version of B is available, then eight inverters can be used to obtain the active-low version. If you think about the conversion operation a while, you ll realize that the most significant bit of the mantissa, m3, is always 1, except in the no-1found case. The 148 has a GS_L output that indicates this case, allowing us to eliminate the multiplexer for m3.

The 148 has active-low outputs, so the exponent bits (E0_L E2_L) are produced in active-low form. Naturally, three inverters could be used to produce an active-high version. Since everything else is active-low, active-low mantissa bits are used too.

Active-high bits are also readily available on the 148 EO_L and the 151 Y_L outputs. Strictly speaking, the multiplexers in Figure 6-3 are drawn incorrectly. The 74x151 symbol can be drawn alternatively as shown in Figure 6-4.

In words, if the multiplexer s data inputs are active low, then the data outputs have an active level opposite that shown in the original symbol. The active-low-data symbol. 74x151. DO NOT COPY DO NOT COPY DO NOT COPY DO NOT COPY DO NOT COPY DO NOT COPY DO NOT COPY DO NOT COPY DO NOT COPY. A B 9 C 4 D0 3 D1 2 D2 1 D3 15 D4 14 D5 13 D6 12 D7 Figure 6-4 Alternate logic symbol for the 74x151 8-input multiplexer. Copyright 1999 by John F. Wakerly Copying Prohibited 6 . Combinational Design Examples DO NOT COPY none for none DO NOT COPY DO NOT COPY DO NOT COPY DO NOT COPY DO NOT COPY DO NOT COPY DO NOT COPY DO NOT COPY. 74x148 74x148 should be pr none none eferred in Figure 6-3, since the active levels of the 151 inputs and outputs would then match their signal names. However, in data transfer and storage applications, designers (and the book) don t always go by the book. It is usually clear from the context that a multiplexer (or a multibit register, in Section 8.

2.5) does not alter the active level of its data. 6.

1.3 Dual-Priority Encoder Quite often MSI building blocks need a little help from their friends ordinary gates to get the job done. In this example, we d like to build a priority encoder that identifies not only the highest but also the second-highest priority asserted signal among a set of eight request inputs.

We ll assume for this example that the request inputs are active low and are named R0_L R7_L, where R0_L has the highest priority. We ll use A2 A0 and AVALID to identify the highest-priority request, where AVALID is asserted only if at least one request input is asserted. We ll use B2 B0 and BVALID to identify the second-highest-priority request, where BVALID is asserted only if at least two request inputs are asserted.

Finding the highest-priority request is easy enough, we can just use a 74x148. To find the second highest-priority request, we can use another 148, but only if we first knock out the highest-priority request before applying the request inputs. This can be done using a decoder to select a signal to knock out, based on A2 A0 and AVALID from the first 148.

These ideas are combined in the solution shown in Figure 6-6. A 74x138 decoder asserts at most one of its eight outputs, corresponding to the highest-priority request input. The outputs are fed to a rank of NAND gates to turn off the highest-priority request.

A trick is used in this solution is to get active-high outputs from the 148s, as shown in Figure 6-5. We can rename the address outputs A2_L A0_L to be active high if we also change the name of the request input that is associated with each output combination. In particular, we complement the bits of the request number.

In the redrawn symbol, request input I0 has the highest priority..
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