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chapter5.fm Page 179 Friday, January 18, 2002 9:01 AM using none tomake none in asp.net web,windows application VB.NET Section 5.2 The Static CMOS Inverter An Intuitive Perspective No direct p none for none ath exists between the supply and ground rails under steady-state operating conditions (this is, when the input and outputs remain constant). The absence of current flow (ignoring leakage currents) means that the gate does not consume any static power. SIDELINE: The above observation, while seemingly obvious, is of crucial importance, and is one of the primary reasons CMOS is the digital technology of choice at present.

The situation was very different in the 1970s and early 1980s. All early microprocessors, such as the Intel 4004, were implemented in a pure NMOS technology. The lack of complementary devices (such as the NMOS and PMOS transistor) in such a technology makes the realization of inverters with zero static power non-trivial.

The resulting static power consumption puts a firm upper bound on the number of gates that can be integrated on a single die; hence the forced move to CMOS in the 1980s, when scaling of the technology allowed for higher integration densities. The nature and the form of the voltage-transfer characteristic (VTC) can be graphically deduced by superimposing the current characteristics of the NMOS and the PMOS devices. Such a graphical construction is traditionally called a load-line plot.

It requires that the I-V curves of the NMOS and PMOS devices are transformed onto a common coordinate set. We have selected the input voltage Vin, the output voltage Vout and the NMOS drain current IDN as the variables of choice. The PMOS I-V relations can be translated into this variable space by the following relations (the subscripts n and p denote the NMOS and PMOS devices, respectively): I DSp = IDSn V GSn = V in ; V GSp = V in V DD V DSn = V out ; V DSp = V out V DD The load-line curves of the PMOS device are obtained by a mirroring around the xaxis and a horizontal shift over VDD.

This procedure is outlined in Figure 5.3, where the subsequent steps to adjust the original PMOS I-V curves to the common coordinate set Vin, Vout and IDn are illustrated..

IDp Vin = 0 Vin = 1.5 IDn IDn Vin = 0 Vin = 1.5 (5.1). VDSp VGSp = 1 VGSp = 2.5 Vin = VDD + VGSp IDn = IDp VDSp Vout Vout = VDD + VDSp Figure 5.3 Tr ansforming PMOS I-V characteristic to a common coordinate set (assuming VDD = 2.5 V).

. chapter5.fm Page 180 Friday, January 18, 2002 9:01 AM THE CMOS INVERTER 5 . IDn Vin = 0 Vin = 2.5 PMOS Vin = 0.5 Vin = 2 NMOS Vin = 1 Vin = 1.5 Vin = 1.5 Vin = 2 Vin = 2.5 Vin = 1.5 Vin = 1 Vin = 1 Vin = 0.5 Vin = 0 Vout Figure 5 none for none .4 Load curves for NMOS and PMOS transistors of the static CMOS inverter (VDD = 2.5 V).

The dots represent the dc operation points for various input voltages.. The resulting load lines are plotted in Figure 5.4. For a dc operating points to be valid, the currents through the NMOS and PMOS devices must be equal.

Graphically, this means that the dc points must be located at the intersection of corresponding load lines. A number of those points (for Vin = 0, 0.5, 1, 1.

5, 2, and 2.5 V) are marked on the graph. As can be observed, all operating points are located either at the high or low output levels.

The VTC of the inverter hence exhibits a very narrow transition zone. This results from the high gain during the switching transient, when both NMOS and PMOS are simultaneously on, and in saturation. In that operation region, a small change in the input voltage results in a large output variation.

All these observations translate into the VTC of Figure 5.5..

Vout 2.5 NMOS off PMOS res NMOS sat PMOS res NMOS sat PMOS sat NMOS res PMOS sat NMOS res PMOS off 2.5 Vin Figure 5.5 VT none for none C of static CMOS inverter, derived from Figure 5.4 (VDD = 2.

5 V). For each operation region, the modes of the transistors are annotated off, res(istive), or sat(urated)..

Before going into the analytical details of the operation of the CMOS inverter, a qualitative analysis of the transient behavior of the gate is appropriate as well. This response is dominated mainly by the output capacitance of the gate, CL, which is com-.
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