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Branch Prediction in Software Include barcode pdf417 in Software Branch Prediction




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4.1 Branch Prediction generate, create pdf417 none on software projects GS1 DataBar Overview 4.1.1 Anat Software pdf417 omy of a Branch Predictor A general predictor model consists of an event source, an information predictor, and, most often, a feedback mechanism.

In the case of branch prediction, we have (Figure 4.1): r Event source: The source of events, that is, branches, is the program dynamic execution. It might contain some predictive information.

The information can be expressed explicitly if the ISA allows it, for example, by having a bit in the opcode indicating the most likely outcome of the branch. Or it can be deduced implicitly: For example, a predictor of the branch s outcome could be linked to whether the branch is forward or backward. Input from a feedback mechanism, such as pro ling, can improve on the prediction at that level.

r Event selection: The events on which predictions will be made are the transfer of control (branch, return from functions) instructions, but, as we shall see, we can attempt predictions on all instructions and never use the predictions for nonbranch instructions. These extraneous predictions are similar in spirit to the computation of branch target addresses in the decode stage of the ve-stage pipeline in Section 2.1.

4. If the instruction was not a branch, the result of the target address calculation was discarded. r Predictor indexing: Prediction schemes access one (or more) table(s), sometimes organized in a cachelike fashion.

Indexing of these tables can use (parts of): the program counter (PC) pointing to the branch instruction on which prediction is performed, the global history of the outcomes of previous branches, the local history of the outcomes of previous branches with the same PC, the history of the path leading to the current instruction, or a combination of some or all of these selectors.. 4.1 Branch Prediction Table 4.1. PDF417 for None Control ow instruction statistics (data from Lee et al.

[LCBAB98]). % Control ow 20.4 18.7 % Cond.

branches (% those taken) 14.9 (46) 13 (39) % Uncond. (% direct) 1.

1 (77) 1.1 (92). Application SPEC95int Desktop % Calls 2.2 2.4 % Returns 2.1 2.1 r Predicto r mechanism: This can be a static scheme (in which case the predictor indexing step does not exist), or a dynamic scheme such as a nite-state machine (saturating counters) or a Markov (correlation) predictor. r Feedback and recovery: The real outcome of the predicted branch is known a few cycles after the prediction. If the prediction was correct, the feedback mechanism should reinforce the predictor s con dence.

If the prediction was erroneous, not only should the predictor state be changed, but also a recovery process has to take place. Note that the feedback can in uence the index (past history) as well as the mechanism (actual prediction) itself. About 20% of executed instructions are control ow instructions: conditional and unconditional branches, function calls, and returns.

Table 4.1 lists some of the characteristics of these control ow instructions for the averages of ve SPEC95 integer benchmarks and ve desktop applications. Although the data are over 10 years old, they are still representative of integer programs, desktop applications, and commercial database queries, with the exception that the percentage of indirect branches in unconditional branches has slightly increased in applications programmed with object-oriented languages.

Conditional branch instructions in these types of programs occur, on the average, every six or seven instructions. In scienti c programs, branches occur slightly less often and are more predictable, because many of the branches are of the endof-loop variety. To put these statistics in perspective, consider a four-way superscalar.

The frequencies of branches shown in Table 4.1 mean that a branch will have to be predicted, on the average, every other cycle. Figure 4.

2 shows the interbranch latencies between prediction requests in a (simulated) four-way out-of-order processor. As.
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