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Front-End: Branch Prediction, Instruction Fetching, and Register Renaming in Software Add pdf417 2d barcode in Software Front-End: Branch Prediction, Instruction Fetching, and Register Renaming




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Front-End: Branch Prediction, Instruction Fetching, and Register Renaming use software pdf417 encoding toget pdf 417 with software GS1-128 I-cache I-TLB Branch Predictor Decoder Register renaming Execution units (a) I nstruction fetch unit using an I-cache Trace cache Trace predictor Branch predictor Decoder I-cache I-TLB. Figure 4.19. Block diagrams of two possible instruction fetch units. Fill unit Register renaming Execution units (b) Instruction fetch unit using a trace cache and B4, for a total o barcode pdf417 for None f 16 instructions. The second, corresponding to the else path, consists of B1, B3, and B4, a total of 15 instructions; merging in the next block would over ow the 16-instruction limit. If we want to store both traces in the trace cache that is, obtain path associativity the tag needs more information than address L1.

One possibility is to record the number of branches and their predicted outcomes. There could be more information stored in an entry if more exibility is desired: for example, target addresses of not-taken branches could be added so that if the branch is indeed taken, fetching of the next trace could be done rapidly. Continuing with the building blocks of Figure 4.

19(b), we see that the contents of a trace are fed to the register renaming stage in the front-end of the pipelining, bypassing the decode stage. This is not always necessarily so that is, the instruction sequence of a trace need not be fully decoded but it is a big advantage for. L1: then B2: 5 instructions else B3: 4 instructions B1: 6 instructions Figure 4.20. Diamond-shape portion of code. B4: 5 instructions 4.2 Instruction Fetching processors with CISC Software barcode pdf417 ISAs such as Intel s IA-32, because the trace can consist of ops rather than full instructions. In a conventional fetch unit, static images of the object code are used to ll the I-cache lines. In contrast, the trace cache lines must be built dynamically.

As in the I-cache, new traces will be inserted when there is a trace cache miss. The sequences of instructions that are used to build the traces can come either from the decoder (the Intel Pentium 4 solution, as shown in Figure 4.19(b)) or from the reorder buffer when instructions commit.

The drawback of lling from the decoder is that traces corresponding to wrong path predictions might be in the trace cache; but they may be useful later, so this is not much of a nuisance. The disadvantage of lling from the reorder buffer is a longer latency in building the traces. Experiments have shown that there is no signi cant difference in performance between these two options.

On a trace cache miss, a ll unit that can hold a trace cache line collects (decoded) instructions fetched from the I-cache until the selection criteria stop the lling. At that point, the new trace is inserted in the trace cache, with (naturally) a possible replacement. On a trace cache hit, it is not sure that all instructions in the trace will be executed, for some of them are dependent on branch outcomes that may differ from one execution to the next.

Therefore, the trace is dispatched both to the next stage in the pipeline and to the ll unit. If all instructions of the trace are executed, no supplementary action is needed. If some branch in the trace has an outcome different from the one that was used to build the trace, the partial trace in the ll unit can be completed by instructions coming from the I-cache, and this newly formed trace can be inserted in the trace cache.

Branch prediction is of fundamental importance for the performance of a conventional fetch unit. In the same vein, an accurate next trace predictor is needed. There are many possible variations.

Part of the prediction can be in the trace line, namely, the starting address of the next trace. An expanded BTB that can make several predictions at a time, say all those that need to be done for a given trace start address, can furnish the remaining information to identify the next trace. An alternate way is to have a predictor basing its information on a path history of past traces and selecting bits from the tags of previous traces to index in the trace predictor table.

In the Intel Pentium 4, the data part of the trace cache entries contains ops. Each line can have up to six ops (recall that the decoder in this processor can decode three ops per cycle). The Pentium 4 trace cache has room for 12 K ops, which, according to Intel designers, means a hit rate equal to that of an 8 to 16 KB I-cache.

In fact, the Pentium 4 does not have an I-cache, and on a trace cache miss, the instructions are fetched from L2. The trace cache has its own BTB of 512 entries that is independent of the 4 K entry BTB used when instructions are fetched from L2. With the same hit rate for the I-cache and the trace cache, the two advantages of an increased fetch bandwidth and of bypassing the decoder seem to be good reasons for a trace cache in an m-way processor with large m and a CISC ISA.

Of course, the trace cache requires more real estate on the chip (see the exercises)..
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