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EXERCISES in Software Integrate pdf417 in Software EXERCISES




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EXERCISES use software barcode pdf417 implement todevelop barcode pdf417 on software About Micro QR Code 1. (Section 4.1.

3) The out barcode pdf417 for None comes of branch execution for a given branch can be seen as a string of bits, 1 for taken and 0 for not taken. For example, the string for the end of loop branch looks like 111 . .

. 1110111 . .

. 1110. .

. . 111 .

. . 1110 .

(a) Consider a diamond structure, that is, code of the form if condition then S1 else S2. What are the prediction accuracies of a 1-bit scheme and of a 2-bit scheme when the conditional expression s value alternates between true and false . Front-End: Branch Prediction, Instruction Fetching, and Register Renaming (b) Find a string where th barcode pdf417 for None e prediction accuracy for a single-bit scheme is 50% and that of a saturating counter scheme as depicted in Figure 4.3 is zero in steady state. Can you think of a programming pattern that ts this type of string (c) Can you modify the state diagram of Figure 4.

3 so that the string you found in part (b) yields a 50% prediction accuracy If so, nd another string for this new state diagram that yields zero accuracy in steady state. Does it correspond to a more likely programming pattern 2. (Section 4.

1.3) Show a state diagram for a scheme where the 2-bit counter is replaced by a 3-bit shift register keeping track of the last three executions of the branch and predicting according to the majority decision of these three executions. Is this a reasonable alternative to a 2-bit saturating counter in terms of performance and cost 3.

(Section 4.1.4) Assume a 3-bit global register (initialized to all 0 s) and a two-level Global global scheme.

(a) How many entries are there in the PHT (b) Show the contents of the global register and of the PHT (where each entry is initialized to the weak not-taken case and follows the state diagram of Figure 4.3), after the following sequence of branch executions has taken place: 1 taken (T) branch, 3 not-taken (NT) branches, 1 T branch, 3 NT branches, 1 T branch. With pred being the prediction and act the actual outcome as per the given string, show your results for each branch, for example, in the form (GR) (pred) (Updated GR) (act) (PHT).

Assume a speculative update for GR and a nonspeculative one for the PHT that occurs before the next branch prediction. Two typical entries could be (i) (000)(0)(000)(1)(01, 01, 01, 01, 01, 01, 01, 11) or (ii) (000)(0)(000)(1)(01, 01, 01, 01, 01, 01, 01, 11); misprediction, restore GPR to (001). 4.

(Section 4.1.5) Assume that the global register is k bits long and that m bits of the PC are used to select among PHTs.

(a) How many bits are used to implement the Global global scheme (b) How many bits are used to implement the Global set scheme 5. (Section 4.1.

5) Assume that k bits of the PC are used to access the BHT, that the local history registers are p bits long, and that m bits of the PC are used to select among PHTs. (a) How many bits are used to implement the Set global scheme (b) How many bits are used to implement the Set set scheme 6. (Section 4.

1.5) The question that microarchitects usually face in the context of a two-level branch predictor is: If I have a certain amount of chip area that I can devote to branch prediction, how should I divide it among the various branch prediction data structures Answer this question assuming a budget of 8 K bits plus a. Exercises 1 13 few extra bits, say less t Software pdf417 han 100. Of course, you should come up with more than one possible design. 7.

(Section 4.1.6) In the repair mechanism for a Global global scheme, a FIFO queue of global registers is accessed at three different times: r When the branch prediction is made (insertion at end of the queue).

r When the branch prediction is correct and the instruction is committed (deletion from the front of the queue). r When the branch prediction is incorrect at the end of the execute stage (deletion of several consecutive entries in the FIFO queue). (a) What extra hardware (tags, pointers, etc.

) must be added so that recovery is possible If there is a maximum of m branches in ight, can the FIFO queue be less than m entries If so, what are the consequences (b) A suggestion is to have each FIFO entry tagged with the PC of the branch it corresponds to. Then the branch would not have to carry a tag. Why is this not possible 8.

(Section 4.1.6) [JSHP97] In the global repair scheme, one can avoid the FIFO queue of saved global registers by using a longer global register.

Indicate how long the global register should be, and describe the implementation structures and the steps necessary for each of the three bulleted points of the previous exercise. 9. (Section 4.

1.7) In the equation giving the branch execution penalty bep of a processor with a BTB and a PHT, we approximated the term Missf mfetch . Give a better formulation, following the entries in Table 4.

2. 10. (Section 4.

1.7) Show that when a special call return stack is implemented, returns corresponding to calls from various locations can be predicted as soon as the return instruction is fetched if the return address is agged appropriately in the BTB. 11.

(Section 4.1.8) There are several possibilities in updating policies for a tournament predictor.

Indicate which ones you would recommend when the local predictor is a bimodal one and the global predictor is of the gshare type. 12. (Section 4.

2.1) Consider an I-cache of 16 KB, two-way set-associative with line size of 32 bytes. Assume a RISC machine with each instruction being 4 bytes.

How much real estate (i.e., how many bits) is needed to implement the line-and-way prediction depicted in Figure 4.

18 when branch prediction elds are available every four instructions How large a direct-mapped BTB could be implemented using the same number of bits 13. (Section 4.2.

2) [PTM99] In addition to the conventional hit rate, other metrics have been identi ed for the evaluation of trace caches, namely fragmentation, duplication, and indexability. Give your own de nitions of these metrics. If one de nes the ef ciency as the ratio (unique instructions)/(total instruction slots), how do fragmentation and duplication relate to ef ciency .

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